The present invention relates to a semiconductor wafer, and more specifically, to a semiconductor wafer with plated wires, and a method of fabricating the same.
Typically, semiconductor fabrication includes forming many integrated circuit (IC) chips on a single wafer. Referring to FIG. 1, IC chips 2 on a single wafer 10 are illustrated. Wafer 10 includes substrate (not shown in FIG. 1) upon which chips 2 are fabricated. Chips 2 are fabricated on wafer 10 by forming numerous layers on wafer 10. As layers are formed, they may be patterned and etched to create various semiconductor structures (i.e., diodes, transistors, inductors, wires, contacts, vias, etc.). Various levels may be created within a single chip 2 by forming a plurality of layers having additional semiconductor structures. Wafer 10 may also include kerf regions 4. Kerf region 4 is the region between chips 2 and can contain dicing channel, electrical test, lithographic measurement, and other structures. Kerf regions 4 typically include materials used in fabrication of chips 2 and facilitate separation of chips 2 such as by dicing. Kerf regions 4 may include a conductive kerf bus 6 as known in the art. Kerf bus 6 may include a metallization on a substrate (not shown in FIG. 1). Kerf bus 6 may run in kerf regions 4 and connect to edges 8 of wafer 10. Once chips 2 are completed, they are tested, diced from wafer 10, and may be connected to external circuity, e.g., a circuit board (not shown).
Generally, the last layer of a chip includes copper wires to facilitate electrical connection of the chip to the circuit board using, for example, one or more of wirebonds, solder bumps, or copper pillars. Conventionally, thin wires were created by traditional damascene processes. The damascene process includes forming a trench in a dielectric layer within a chip, depositing a liner/seed layer to coat the trench, filling the trench with metal, and then polishing the metal to form a recessed wire. These conventional damascene processes have wire heights of approximately 1 micron or less. Recently, thicker wires of approximately 2 to 12 microns in height (thickness) have been used to create intralevel ultra-low resistance structures as well as inductors on the chip. More specifically, these thicker wires are approximately 6 microns thick. However, the conventional damascene process is not advantageous for fabricating these thicker wires because it is complex and expensive. Additionally, fabrication of thick wires was traditionally performed on the circuit board. More recently, the wires have been fabricated on the wafer to reduce cost and improve performance.